Kernel-3.10.0-957.el7_sdhci-cadence

  • Cadence SD/SDIO/eMMC Host Controller

Required properties:

  • compatible: should be one of the following:
    “cdns,sd4hc” - default of the IP
    “socionext,uniphier-sd4hc” - for Socionext UniPhier SoCs
  • reg: offset and length of the register set for the device.
  • interrupts: a single interrupt specifier.
  • clocks: phandle to the input clock.

Optional properties:
For eMMC configuration, supported speed modes are not indicated by the SDHCI
Capabilities Register. Instead, the following properties should be specified
if supported. See mmc.txt for details.

  • mmc-ddr-1_8v
  • mmc-ddr-1_2v
  • mmc-hs200-1_8v
  • mmc-hs200-1_2v
  • mmc-hs400-1_8v
  • mmc-hs400-1_2v

Example:
emmc: sdhci@5a000000 {
compatible = “socionext,uniphier-sd4hc”, “cdns,sd4hc”;
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
clocks = <&clk 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
};