Kernel-3.10.0-957.el7_mdio-mux-mmioreg

Properties for an MDIO bus multiplexer controlled by a memory-mapped device

This is a special case of a MDIO bus multiplexer. A memory-mapped device,
like an FPGA, is used to control which child bus is connected. The mdio-mux
node must be a child of the memory-mapped device. The driver currently only
supports devices with eight-bit registers.

Required properties in addition to the generic multiplexer properties:

• compatible : string, must contain “mdio-mux-mmioreg”

• reg : integer, contains the offset of the register that controls the bus
  multiplexer. The size field in the ‘reg’ property is the size of
  register, and must therefore be 1.

• mux-mask : integer, contains an eight-bit mask that specifies which
  bits in the register control the actual bus multiplexer. The
  ‘reg’ property of each child mdio-mux node must be constrained by
  this mask.

Example:

The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.
For the “EMI2” MDIO bus, register 9 (BRDCFG1) controls the mux on that bus.
A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on
BRDCFG1 that control the actual mux.

/* The FPGA node */
fpga: board-control@3,0 {
    #address-cells = <1>;
    #size-cells = <1>;
    compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
    reg = <3 0 0x30>;
    ranges = <0 3 0 0x30>;

    mdio-mux-emi2 {
        compatible = "mdio-mux-mmioreg", "mdio-mux";
        mdio-parent-bus = <&xmdio0>;
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <9 1>; // BRDCFG1
        mux-mask = <0x6>; // EMI2

        emi2_slot1: mdio@0 {    // Slot 1 XAUI (FM2)
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;

            phy_xgmii_slot1: ethernet-phy@0 {
                compatible = "ethernet-phy-ieee802.3-c45";
                reg = <4>;
            };
        };

        emi2_slot2: mdio@2 {    // Slot 2 XAUI (FM1)
            reg = <2>;
            #address-cells = <1>;
            #size-cells = <0>;

            phy_xgmii_slot2: ethernet-phy@4 {
                compatible = "ethernet-phy-ieee802.3-c45";
                reg = <0>;
            };
        };
    };
};

/* The parent MDIO bus. */
xmdio0: mdio@f1000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "fsl,fman-xmdio";
    reg = <0xf1000 0x1000>;
    interrupts = <100 1 0 0>;
};