Kernel-3.10.0-957.el7_mdio-mux-gpio

Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.

This is a special case of a MDIO bus multiplexer. One or more GPIO
lines are used to control which child bus is connected.

Required properties in addition to the generic multiplexer properties:

• compatible : mdio-mux-gpio.
• gpios : GPIO specifiers for each GPIO line. One or more must be specified.

Example :

/* The parent MDIO bus. */
smi1: mdio@1180000001900 {
    compatible = "cavium,octeon-3860-mdio";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x11800 0x00001900 0x0 0x40>;
};

/*
   An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
   pair of GPIO lines.  Child busses 2 and 3 populated with 4
   PHYs each.
 */
mdio-mux {
    compatible = "mdio-mux-gpio";
    gpios = <&gpio1 3 0>, <&gpio1 4 0>;
    mdio-parent-bus = <&smi1>;
    #address-cells = <1>;
    #size-cells = <0>;

    mdio@2 {
        reg = <2>;
        #address-cells = <1>;
        #size-cells = <0>;

        phy11: ethernet-phy@1 {
            reg = <1>;
            compatible = "marvell,88e1149r";
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <10 8>; /* Pin 10, active low */
        };
        phy12: ethernet-phy@2 {
            reg = <2>;
            compatible = "marvell,88e1149r";
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <10 8>; /* Pin 10, active low */
        };
        phy13: ethernet-phy@3 {
            reg = <3>;
            compatible = "marvell,88e1149r";
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <10 8>; /* Pin 10, active low */
        };
        phy14: ethernet-phy@4 {
            reg = <4>;
            compatible = "marvell,88e1149r";
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <10 8>; /* Pin 10, active low */
        };
    };

    mdio@3 {
        reg = <3>;
        #address-cells = <1>;
        #size-cells = <0>;

        phy21: ethernet-phy@1 {
            reg = <1>;
            compatible = "marvell,88e1149r";
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <12 8>; /* Pin 12, active low */
        };
        phy22: ethernet-phy@2 {
            reg = <2>;
            compatible = "marvell,88e1149r";
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <12 8>; /* Pin 12, active low */
        };
        phy23: ethernet-phy@3 {
            reg = <3>;
            compatible = "marvell,88e1149r";
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <12 8>; /* Pin 12, active low */
        };
        phy24: ethernet-phy@4 {
            reg = <4>;
            compatible = "marvell,88e1149r";
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <12 8>; /* Pin 12, active low */
        };
    };
};