Kernel-4.18.0-80.el8_xilinx-pcie

• Xilinx AXI PCIe Root Port Bridge DT description

Required properties:

• #address-cells: Address representation for root ports, set to <3>
• #size-cells: Size representation for root ports, set to <2>
• #interrupt-cells: specifies the number of cells needed to encode an
  interrupt source. The value must be 1.
• compatible: Should contain “xlnx,axi-pcie-host-1.00.a”
• reg: Should contain AXI PCIe registers location and length
• device_type: must be “pci”
• interrupts: Should contain AXI PCIe interrupt
• interrupt-map-mask,
  interrupt-map: standard PCI properties to define the mapping of the
  PCI interface to interrupt numbers.
• ranges: ranges for the PCI memory regions (I/O space region is not
  supported by hardware)
  Please refer to the standard PCI bus binding document for a more
  detailed explanation

Optional properties for Zynq/Microblaze:

• bus-range: PCI bus numbers covered

Interrupt controller child node
+++++++++++++++++++++++++++++++
Required properties:

• interrupt-controller: identifies the node as an interrupt controller
• #address-cells: specifies the number of cells needed to encode an
  address. The value must be 0.
• #interrupt-cells: specifies the number of cells needed to encode an
  interrupt source. The value must be 1.

NOTE:
The core provides a single interrupt for both INTx/MSI messages. So,
created a interrupt controller node to support ‘interrupt-map’ DT
functionality. The driver will create an IRQ domain for this map, decode
the four INTx interrupts in ISR and route them to this domain.

Example:
++++++++
Zynq:
pci_express: axi-pcie@50000000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
compatible = “xlnx,axi-pcie-host-1.00.a”;
reg = < 0x50000000 0x1000000 >;
device_type = “pci”;
interrupts = < 0 52 4 >;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 1>,
<0 0 0 2 &pcie_intc 2>,
<0 0 0 3 &pcie_intc 3>,
<0 0 0 4 &pcie_intc 4>;
ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;

    pcie_intc: interrupt-controller {
        interrupt-controller;
        #address-cells = <0>;
        #interrupt-cells = <1>;
    };
};

Microblaze:
pci_express: axi-pcie@10000000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
compatible = “xlnx,axi-pcie-host-1.00.a”;
reg = <0x10000000 0x4000000>;
device_type = “pci”;
interrupt-parent = <&microblaze_0_intc>;
interrupts = <1 2>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 1>,
<0 0 0 2 &pcie_intc 2>,
<0 0 0 3 &pcie_intc 3>,
<0 0 0 4 &pcie_intc 4>;
ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;

    pcie_intc: interrupt-controller {
        interrupt-controller;
        #address-cells = <0>;
        #interrupt-cells = <1>;
    };

};