Kernel-4.18.0-80.el8_sata-uctl

• UCTL SATA controller glue

UCTL is the bridge unit between the I/O interconnect (an internal bus)
and the SATA AHCI host controller (UAHC). It performs the following functions:
- provides interfaces for the applications to access the UAHC AHCI
registers on the CN71XX I/O space.
- provides a bridge for UAHC to fetch AHCI command table entries and data
buffers from Level 2 Cache.
- posts interrupts to the CIU.
- contains registers that:
- control the behavior of the UAHC
- control the clock/reset generation to UAHC
- control endian swapping for all UAHC registers and DMA accesses

Properties:

• compatible: “cavium,octeon-7130-sata-uctl”

  Compatibility with the cn7130 SOC.

• reg: The base address of the UCTL register bank.

• #address-cells, #size-cells, ranges and dma-ranges must be present and hold
  suitable values to map all child nodes.

Example:

uctl@118006c000000 {
    compatible = "cavium,octeon-7130-sata-uctl";
    reg = <0x11800 0x6c000000 0x0 0x100>;
    ranges; /* Direct mapping */
    dma-ranges;
    #address-cells = <2>;
    #size-cells = <2>;

    sata: sata@16c0000000000 {
        compatible = "cavium,octeon-7130-ahci";
        reg = <0x16c00 0x00000000 0x0 0x200>;
        interrupt-parent = <&cibsata>;
        interrupts = <2 4>; /* Bit: 2, level */
    };
};