Kernel-4.18.0-80.el8_renesas,rcar-gen2-cpg-clocks

• Renesas R-Car Gen2 Clock Pulse Generator (CPG)

The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
and several fixed ratio dividers.
The CPG also provides a Clock Domain for SoC devices, in combination with the
CPG Module Stop (MSTP) Clocks.

Required Properties:

• compatible: Must be one of

  • “renesas,r8a7790-cpg-clocks” for the r8a7790 CPG
  • “renesas,r8a7791-cpg-clocks” for the r8a7791 CPG
  • “renesas,r8a7792-cpg-clocks” for the r8a7792 CPG
  • “renesas,r8a7793-cpg-clocks” for the r8a7793 CPG
  • “renesas,r8a7794-cpg-clocks” for the r8a7794 CPG
    and “renesas,rcar-gen2-cpg-clocks” as a fallback.

• reg: Base address and length of the memory resource used by the CPG

• clocks: References to the parent clocks: first to the EXTAL clock, second
  to the USB_EXTAL clock

• #clock-cells: Must be 1

• clock-output-names: The names of the clocks. Supported clocks are “main”,
  “pll0”, “pll1”, “pll3”, “lb”, “qspi”, “sdh”, “sd0”, “sd1”, “z”, “rcan”, and
  “adsp”

• #power-domain-cells: Must be 0

SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
through an MSTP clock should refer to the CPG device node in their
“power-domains” property, as documented by the generic PM domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt.

Examples

• CPG device node:

  cpg_clocks: cpg_clocks@e6150000 {

  compatible = "renesas,r8a7790-cpg-clocks",
           "renesas,rcar-gen2-cpg-clocks";
  reg = <0 0xe6150000 0 0x1000>;
  clocks = <&extal_clk &usb_extal_clk>;
  #clock-cells = <1>;
  clock-output-names = "main", "pll0, "pll1", "pll3",
               "lb", "qspi", "sdh", "sd0", "sd1", "z",
               "rcan", "adsp";
  #power-domain-cells = <0>;
  

  };

• CPG/MSTP Clock Domain member device node:

  thermal@e61f0000 {

  compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
  reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
  interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
  clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
  power-domains = <&cpg_clocks>;
  

  };