Kernel-4.18.0-80.el8_renesas,lvds

Renesas R-Car LVDS Encoder

These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
Gen2, R-Car Gen3 and RZ/G SoCs.

Required properties:

• compatible : Shall contain one of

  • “renesas,r8a7743-lvds” for R8A7743 (RZ/G1M) compatible LVDS encoders
  • “renesas,r8a7790-lvds” for R8A7790 (R-Car H2) compatible LVDS encoders
  • “renesas,r8a7791-lvds” for R8A7791 (R-Car M2-W) compatible LVDS encoders
  • “renesas,r8a7793-lvds” for R8A7793 (R-Car M2-N) compatible LVDS encoders
  • “renesas,r8a7795-lvds” for R8A7795 (R-Car H3) compatible LVDS encoders
  • “renesas,r8a7796-lvds” for R8A7796 (R-Car M3-W) compatible LVDS encoders
  • “renesas,r8a77970-lvds” for R8A77970 (R-Car V3M) compatible LVDS encoders
  • “renesas,r8a77995-lvds” for R8A77995 (R-Car D3) compatible LVDS encoders

• reg: Base address and length for the memory-mapped registers

• clocks: A phandle + clock-specifier pair for the functional clock

• resets: A phandle + reset specifier for the module reset

Required nodes:

The LVDS encoder has two video ports. Their connections are modelled using the
OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.

• Video port 0 corresponds to the parallel RGB input
• Video port 1 corresponds to the LVDS output

Each port shall have a single endpoint.

Example:

lvds0: lvds@feb90000 {
    compatible = "renesas,r8a7790-lvds";
    reg = <0 0xfeb90000 0 0x1c>;
    clocks = <&cpg CPG_MOD 726>;
    resets = <&cpg 726>;

    ports {
        #address-cells = <1>;
        #size-cells = <0>;

        port@0 {
            reg = <0>;
            lvds0_in: endpoint {
                remote-endpoint = <&du_out_lvds0>;
            };
        };
        port@1 {
            reg = <1>;
            lvds0_out: endpoint {
            };
        };
    };
};