Kernel-4.18.0-80.el8_qcom_hidma_mgmt

Qualcomm Technologies HIDMA Management interface

Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
memcpy and memset capabilities. It has been designed for virtualized
environments.

Each HIDMA HW instance consists of multiple DMA channels. These channels
share the same bandwidth. The bandwidth utilization can be partitioned
among channels based on the priority and weight assignments.

There are only two priority levels and 15 weigh assignments possible.

Other parameters here determine how much of the system bus this HIDMA
instance can use like maximum read/write request and number of bytes to
read/write in a single burst.

Main node required properties:

• compatible: “qcom,hidma-mgmt-1.0”;
• reg: Address range for DMA device
• dma-channels: Number of channels supported by this DMA controller.
• max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
  occupy the bus for in a single transaction. A memcpy requested is
  fragmented to multiples of this amount. This parameter is used while
  writing into destination memory. Setting this value incorrectly can
  starve other peripherals in the system.
• max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
  occupy the bus for in a single transaction. A memcpy request is
  fragmented to multiples of this amount. This parameter is used while
  reading the source memory. Setting this value incorrectly can starve
  other peripherals in the system.
• max-write-transactions: This value is how many times a write burst is
  applied back to back while writing to the destination before yielding
  the bus.
• max-read-transactions: This value is how many times a read burst is
  applied back to back while reading the source before yielding the bus.
• channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
  Once a reset is applied to the HW, HW starts a timer for reset operation
  to confirm. If reset is not completed within this time, HW reports reset
  failure.

Sub-nodes:

HIDMA has one or more DMA channels that are used to move data from one
memory location to another.

When the OS is not in control of the management interface (i.e. it’s a guest),
the channel nodes appear on their own, not under a management node.

Required properties:

• compatible: must contain “qcom,hidma-1.0” for initial HW or
  “qcom,hidma-1.1”/“qcom,hidma-1.2” for MSI capable HW.
• reg: Addresses for the transfer and event channel
• interrupts: Should contain the event interrupt
• desc-count: Number of asynchronous requests this channel can handle
• iommus: required a iommu node

Optional properties for MSI:

• msi-parent : See the generic MSI binding described in
  devicetree/bindings/interrupt-controller/msi.txt for a description of the
  msi-parent property.

Example:

Hypervisor OS configuration:

hidma-mgmt@f9984000 = {
    compatible = "qcom,hidma-mgmt-1.0";
    reg = <0xf9984000 0x15000>;
    dma-channels = <6>;
    max-write-burst-bytes = <1024>;
    max-read-burst-bytes = <1024>;
    max-write-transactions = <31>;
    max-read-transactions = <31>;
    channel-reset-timeout-cycles = <0x500>;

    hidma_24: dma-controller@5c050000 {
        compatible = "qcom,hidma-1.0";
        reg = <0 0x5c050000 0x0 0x1000>,
              <0 0x5c0b0000 0x0 0x1000>;
        interrupts = <0 389 0>;
        desc-count = <10>;
        iommus = <&system_mmu>;
    };
};

Guest OS configuration:

hidma_24: dma-controller@5c050000 {
    compatible = "qcom,hidma-1.0";
    reg = <0 0x5c050000 0x0 0x1000>,
          <0 0x5c0b0000 0x0 0x1000>;
    interrupts = <0 389 0>;
    desc-count = <10>;
    iommus = <&system_mmu>;
};