Kernel-4.18.0-80.el8_pwm-fsl-ft

Freescale FlexTimer Module (FTM) PWM controller

The same FTM PWM device can have a different endianness on different SoCs. The
device tree provides a property to describing this so that an operating system
device driver can handle all variants of the device. Refer to the table below
for the endianness of the FTM PWM block as integrated into the existing SoCs:

SoC     | FTM-PWM endianness
--------+-------------------
Vybrid  | LE
LS1     | BE
LS2     | LE

Please see ../regmap/regmap.txt for more detail about how to specify endian
modes in device tree.

Required properties:

• compatible: Should be “fsl,vf610-ftm-pwm”.
• reg: Physical base address and length of the controller’s registers
• #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
  the cells format.
• clock-names: Should include the following module clock source entries:
  “ftm_sys” (module clock, also can be used as counter clock),
  “ftm_ext” (external counter clock),
  “ftm_fix” (fixed counter clock),
  “ftm_cnt_clk_en” (external and fixed counter clock enable/disable).
• clocks: Must contain a phandle and clock specifier for each entry in
  clock-names, please see clock/clock-bindings.txt for details of the property
  values.
• pinctrl-names: Must contain a “default” entry.
• pinctrl-NNN: One property must exist for each entry in pinctrl-names.
  See pinctrl/pinctrl-bindings.txt for details of the property values.
• big-endian: Boolean property, required if the FTM PWM registers use a big-
  endian rather than little-endian layout.

Example:

pwm0: pwm@40038000 {
compatible = “fsl,vf610-ftm-pwm”;
reg = <0x40038000 0x1000>;
#pwm-cells = <3>;
clock-names = “ftm_sys”, “ftm_ext”,
“ftm_fix”, “ftm_cnt_clk_en”;
clocks = <&clks VF610_CLK_FTM0>,
<&clks VF610_CLK_FTM0_EXT_SEL>,
<&clks VF610_CLK_FTM0_FIX_SEL>,
<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
pinctrl-names = “default”;
pinctrl-0 = <&pinctrl_pwm0_1>;
big-endian;
};