Kernel-4.18.0-80.el8_mtk-quadspi

• Serial NOR flash controller for MTK MT81xx (and similar)

Required properties:

• compatible: For mt8173, compatible should be “mediatek,mt8173-nor”,

      and it's the fallback compatible for other Soc.
      For every other SoC, should contain both the SoC-specific compatible
      string and "mediatek,mt8173-nor".
      The possible values are:
      "mediatek,mt2701-nor", "mediatek,mt8173-nor"
      "mediatek,mt2712-nor", "mediatek,mt8173-nor"
      "mediatek,mt7622-nor", "mediatek,mt8173-nor"
      "mediatek,mt7623-nor", "mediatek,mt8173-nor"
      "mediatek,mt8173-nor"
  

• reg: physical base address and length of the controller’s register
• clocks: the phandle of the clocks needed by the nor controller
• clock-names: the names of the clocks

      the clocks should be named "spi" and "sf". "spi" is used for spi bus,
      and "sf" is used for controller, these are the clocks witch
      hardware needs to enabling nor flash and nor flash controller.
      See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
  

• #address-cells: should be <1>
• #size-cells: should be <0>

The SPI flash must be a child of the nor_flash node and must have a
compatible property. Also see jedec,spi-nor.txt.

Required properties:

• compatible: May include a device-specific string consisting of the manufacturer

      and name of the chip. Must also include "jedec,spi-nor" for any
      SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F).
  

• reg : Chip-Select number

Example:

nor_flash: spi@1100d000 {
compatible = “mediatek,mt8173-nor”;
reg = <0 0x1100d000 0 0xe0>;
clocks = <&pericfg CLK_PERI_SPI>,
<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
clock-names = “spi”, “sf”;
#address-cells = <1>;
#size-cells = <0>;

flash@0 {
    compatible = "jedec,spi-nor";
    reg = <0>;
};

};