Kernel-4.18.0-80.el8_l2ecc

Calxeda Highbank L2 cache ECC

Properties:

• compatible : Should be “calxeda,hb-sregs-l2-ecc”
• reg : Address and size for ECC error interrupt clear registers.
• interrupts : Should be single bit error interrupt, then double bit error
  interrupt.

Example:

sregs@fff3c200 {
    compatible = "calxeda,hb-sregs-l2-ecc";
    reg = <0xfff3c200 0x100>;
    interrupts = <0 71 4  0 72 4>;
};