Kernel-4.18.0-80.el8_hisilicon-femac

Hisilicon Fast Ethernet MAC controller

Required properties:

• compatible: should contain one of the following version strings:
  • “hisilicon,hisi-femac-v1”
  • “hisilicon,hisi-femac-v2”
    and the soc string “hisilicon,hi3516cv300-femac”.
• reg: specifies base physical address(s) and size of the device registers.
  The first region is the MAC core register base and size.
  The second region is the global MAC control register.
• interrupts: should contain the MAC interrupt.
• clocks: A phandle to the MAC main clock.
• resets: should contain the phandle to the MAC reset signal(required) and
  the PHY reset signal(optional).
• reset-names: should contain the reset signal name “mac”(required)
  and “phy”(optional).
• mac-address: see ethernet.txt [1].
• phy-mode: see ethernet.txt [1].
• phy-handle: see ethernet.txt [1].
• hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
  The 1st cell is reset pre-delay in micro seconds.
  The 2nd cell is reset pulse in micro seconds.
  The 3rd cell is reset post-delay in micro seconds.

[1] Documentation/devicetree/bindings/net/ethernet.txt

Example:
hisi_femac: ethernet@10090000 {
compatible = “hisilicon,hi3516cv300-femac”,”hisilicon,hisi-femac-v2”;
reg = <0x10090000 0x1000>,<0x10091300 0x200>;
interrupts = <12>;
clocks = <&crg HI3518EV200_ETH_CLK>;
resets = <&crg 0xec 0>,<&crg 0xec 3>;
reset-names = “mac”,”phy”;
mac-address = [00 00 00 00 00 00];
phy-mode = “mii”;
phy-handle = <&phy0>;
hisilicon,phy-reset-delays-us = <10000 20000 20000>;
};