Kernel-4.18.0-80.el8_gpio-mvebu

• Marvell EBU GPIO controller

Required properties:

• compatible : Should be “marvell,orion-gpio”, “marvell,mv78200-gpio”,
  “marvell,armadaxp-gpio” or “marvell,armada-8k-gpio”.

  “marvell,orion-gpio” should be used for Orion, Kirkwood, Dove,
  Discovery (except MV78200) and Armada 370. “marvell,mv78200-gpio”
  should be used for the Discovery MV78200.

  “marvel,armadaxp-gpio” should be used for all Armada XP SoCs
  (MV78230, MV78260, MV78460).

  “marvell,armada-8k-gpio” should be used for the Armada 7K and 8K
  SoCs (either from AP or CP), see
  Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
  and
  Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
  for specific details about the offset property.

• reg: Address and length of the register set for the device. Only one
  entry is expected, except for the “marvell,armadaxp-gpio” variant
  for which two entries are expected: one for the general registers,
  one for the per-cpu registers. Not used for marvell,armada-8k-gpio.

• interrupts: The list of interrupts that are used for all the pins
  managed by this GPIO bank. There can be more than one interrupt
  (example: 1 interrupt per 8 pins on Armada XP, which means 4
  interrupts per bank of 32 GPIOs).

• interrupt-controller: identifies the node as an interrupt controller

• #interrupt-cells: specifies the number of cells needed to encode an
  interrupt source. Should be two.
  The first cell is the GPIO number.
  The second cell is used to specify flags:
  bits[3:0] trigger type and level flags:

  1 = low-to-high edge triggered.
  2 = high-to-low edge triggered.
  4 = active high level-sensitive.
  8 = active low level-sensitive.
  

• gpio-controller: marks the device node as a gpio controller

• ngpios: number of GPIOs this controller has

• #gpio-cells: Should be two. The first cell is the pin number. The
  second cell is reserved for flags, unused at the moment.

Optional properties:

In order to use the GPIO lines in PWM mode, some additional optional
properties are required.

• compatible: Must contain “marvell,armada-370-gpio”

• reg: an additional register set is needed, for the GPIO Blink
  Counter on/off registers.

• reg-names: Must contain an entry “pwm” corresponding to the
  additional register range needed for PWM operation.

• #pwm-cells: Should be two. The first cell is the GPIO line number. The
  second cell is the period in nanoseconds.

• clocks: Must be a phandle to the clock for the GPIO controller.

Example:

    gpio0: gpio@d0018100 {
        compatible = "marvell,armadaxp-gpio";
        reg = <0xd0018100 0x40>,
            <0xd0018800 0x30>;
        ngpios = <32>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <16>, <17>, <18>, <19>;
    };

    gpio1: gpio@18140 {
        compatible = "marvell,armada-370-gpio";
        reg = <0x18140 0x40>, <0x181c8 0x08>;
        reg-names = "gpio", "pwm";
        ngpios = <17>;
        gpio-controller;
        #gpio-cells = <2>;
        #pwm-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <87>, <88>, <89>;
        clocks = <&coreclk 0>;
    };