GPIO assisted NAND flash
The GPIO assisted NAND flash uses a memory mapped interface to
read/write the NAND commands and data and GPIO pins for the control
signals.
Required properties:
- compatible : “gpio-control-nand”
- reg : should specify localbus chip select and size used for the chip. The
resource describes the data bus connected to the NAND flash and all accesses
are made in native endianness. - #address-cells, #size-cells : Must be present if the device has sub-nodes
representing partitions. - gpios : Specifies the GPIO pins to control the NAND device. The order of
GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.
Optional properties:
- bank-width : Width (in bytes) of the device. If not present, the width
defaults to 1 byte. - chip-delay : chip dependent delay for transferring data from array to
read registers (tR). If not present then a default of 20us is used. - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
location used to guard against bus reordering with regards to accesses to
the GPIO’s and the NAND flash data bus. If present, then after changing
GPIO state and before and after command byte writes, this register will be
read to ensure that the GPIO accesses have completed.
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
Examples:
gpio-nand@1,0 {
compatible = “gpio-control-nand”;
reg = <1 0x0000 0x2>;
#address-cells = <1>;
#size-cells = <1>;
gpios = <&banka 1 0>, /* RDY /
<0>, / nCE /
<&banka 3 0>, / ALE /
<&banka 4 0>, / CLE /
<0>; / nWP */
partition@0 {
...
};
};
