Kernel-4.18.0-80.el8_fsl-sec6

SEC 6 is as Freescale’s Cryptographic Accelerator and Assurance Module (CAAM).
Currently Freescale powerpc chip C29X is embedded with SEC 6.
SEC 6 device tree binding include:
-SEC 6 Node
-Job Ring Node
-Full Example

=====================================================================
SEC 6 Node

Description

Node defines the base address of the SEC 6 block.
This block specifies the address range of all global
configuration registers for the SEC 6 block.
For example, In C293, we could see three SEC 6 node.

PROPERTIES

• compatible
  Usage: required
  Value type:
  Definition: Must include “fsl,sec-v6.0”.

• fsl,sec-era
  Usage: optional
  Value type:
  Definition: A standard property. Define the ‘ERA’ of the SEC

   device.
  

• #address-cells
  Usage: required
  Value type:
  Definition: A standard property. Defines the number of cells

    for representing physical addresses in child nodes.
  

• #size-cells
  Usage: required
  Value type:
  Definition: A standard property. Defines the number of cells

    for representing the size of physical addresses in
    child nodes.
  

• reg
  Usage: required
  Value type:
  Definition: A standard property. Specifies the physical

   address and length of the SEC 6 configuration registers.
  

• ranges
  Usage: required
  Value type:
  Definition: A standard property. Specifies the physical address

    range of the SEC 6.0 register space (-SNVS not included).  A
    triplet that includes the child address, parent address, &
    length.
  

  Note: All other standard properties (see the Devicetree Specification)
  are allowed but are optional.

EXAMPLE
crypto@a0000 {
compatible = “fsl,sec-v6.0”;
fsl,sec-era = <6>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0xa0000 0x20000>;
ranges = <0 0xa0000 0x20000>;
};

=====================================================================
Job Ring (JR) Node

Child of the crypto node defines data processing interface to SEC 6
across the peripheral bus for purposes of processing
cryptographic descriptors. The specified address
range can be made visible to one (or more) cores.
The interrupt defined for this node is controlled within
the address range of this node.

• compatible
  Usage: required
  Value type:
  Definition: Must include “fsl,sec-v6.0-job-ring”.

• reg
  Usage: required
  Value type:
  Definition: Specifies a two JR parameters: an offset from

     the parent physical address and the length the JR registers.
  

• interrupts
  Usage: required
  Value type:
  Definition: Specifies the interrupts generated by this

    device.  The value of the interrupts property
    consists of one interrupt specifier. The format
    of the specifier is defined by the binding document
    describing the node's interrupt parent.
  

EXAMPLE
jr@1000 {
compatible = “fsl,sec-v6.0-job-ring”;
reg = <0x1000 0x1000>;
interrupts = <49 2 0 0>;
};

===================================================================
Full Example

Since some chips may contain more than one SEC, the dtsi contains
only the node contents, not the node itself. A chip using the SEC
should include the dtsi inside each SEC node. Example:

In qoriq-sec6.0.dtsi:

compatible = "fsl,sec-v6.0";
fsl,sec-era = <6>;
#address-cells = <1>;
#size-cells = <1>;

jr@1000 {
    compatible = "fsl,sec-v6.0-job-ring",
             "fsl,sec-v5.2-job-ring",
             "fsl,sec-v5.0-job-ring",
             "fsl,sec-v4.4-job-ring",
             "fsl,sec-v4.0-job-ring";
    reg       = <0x1000 0x1000>;
};

jr@2000 {
    compatible = "fsl,sec-v6.0-job-ring",
             "fsl,sec-v5.2-job-ring",
             "fsl,sec-v5.0-job-ring",
             "fsl,sec-v4.4-job-ring",
             "fsl,sec-v4.0-job-ring";
    reg       = <0x2000 0x1000>;
};

In the C293 device tree, we add the include of public property:

crypto@a0000 {
    /include/ "qoriq-sec6.0.dtsi"
}

crypto@a0000 {
    reg = <0xa0000 0x20000>;
    ranges = <0 0xa0000 0x20000>;

    jr@1000 {
        interrupts = <49 2 0 0>;
    };

    jr@2000 {
        interrupts = <50 2 0 0>;
    };
};