Kernel-4.18.0-80.el8_fsl,imx7d-pinctrl

published: updated: Kernel_4.18.0-80.el8_内核文档
  • Freescale i.MX7 Dual IOMUX Controller

iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
power state retention capabilities on gpios that are part of iomuxc-lpsr
(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
mux and pad control settings, it shares the input select register from main
iomuxc controller for daisy chain settings, the fsl,input-sel property extends
fsl,imx-pinctrl driver to support iomuxc-lpsr controller.

iomuxc_lpsr: iomuxc-lpsr@302c0000 {
compatible = “fsl,imx7d-iomuxc-lpsr”;
reg = <0x302c0000 0x10000>;
fsl,input-sel = <&iomuxc>;
};

iomuxc: iomuxc@30330000 {
compatible = “fsl,imx7d-iomuxc”;
reg = <0x30330000 0x10000>;
};

Peripherals using pads from iomuxc-lpsr support low state retention power
state, under LPSR mode GPIO’s state of pads are retain.

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:

  • compatible: “fsl,imx7d-iomuxc” for main IOMUXC controller, or
    “fsl,imx7d-iomuxc-lpsr” for Low Power State Retention IOMUXC controller.
  • fsl,pins: each entry consists of 6 integers and represents the mux and config
    setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in
    imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
    the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
    Reference Manual for detailed CONFIG settings.
  • fsl,input-sel: required property for iomuxc-lpsr controller, this property is
    a phandle for main iomuxc controller which shares the input select register for
    daisy chain settings.

CONFIG bits definition:
PAD_CTL_PUS_100K_DOWN (0 << 5)
PAD_CTL_PUS_5K_UP (1 << 5)
PAD_CTL_PUS_47K_UP (2 << 5)
PAD_CTL_PUS_100K_UP (3 << 5)
PAD_CTL_PUE (1 << 4)
PAD_CTL_HYS (1 << 3)
PAD_CTL_SRE_SLOW (1 << 2)
PAD_CTL_SRE_FAST (0 << 2)
PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)

Examples:
While iomuxc-lpsr is intended to be used by dedicated peripherals to take
advantages of LPSR power mode, is also possible that an IP to use pads from
any of the iomux controllers. For example the I2C1 IP can use SCL pad from
iomuxc-lpsr controller and SDA pad from iomuxc controller as:

i2c1: i2c@30a20000 {
pinctrl-names = “default”;
pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
};

iomuxc-lpsr@302c0000 {
compatible = “fsl,imx7d-iomuxc-lpsr”;
reg = <0x302c0000 0x10000>;
fsl,input-sel = <&iomuxc>;

pinctrl_i2c1_1: i2c1grp-1 {
    fsl,pins = <
        MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
    >;
};

};

iomuxc@30330000 {
compatible = “fsl,imx7d-iomuxc”;
reg = <0x30330000 0x10000>;

pinctrl_i2c1_2: i2c1grp-2 {
    fsl,pins = <
        MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
    >;
};

};

oosTech by Sam Lee