Kernel-4.18.0-80.el8_designware-pcie

• Synopsys DesignWare PCIe interface

Required properties:

• compatible:
  “snps,dw-pcie” for RC mode;
  “snps,dw-pcie-ep” for EP mode;
• reg: Should contain the configuration address space.
• reg-names: Must be “config” for the PCIe configuration space.
  (The old way of getting the configuration address space from “ranges”
  is deprecated and should be avoided.)
• num-lanes: number of lanes to use
  RC mode:
• #address-cells: set to <3>
• #size-cells: set to <2>
• device_type: set to “pci”
• ranges: ranges for the PCI memory and I/O regions
• #interrupt-cells: set to <1>
• interrupt-map-mask and interrupt-map: standard PCI
  properties to define the mapping of the PCIe interface to interrupt
  numbers.
  EP mode:
• num-ib-windows: number of inbound address translation windows
• num-ob-windows: number of outbound address translation windows

Optional properties:

• num-lanes: number of lanes to use (this property should be specified unless
  the link is brought already up in BIOS)
• reset-gpio: GPIO pin number of power good signal
• clocks: Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
• clock-names: Must include the following entries:
  • “pcie”
  • “pcie_bus”
    RC mode:
• num-viewport: number of view ports configured in hardware. If a platform
  does not specify it, the driver assumes 2.
• bus-range: PCI bus numbers covered (it is recommended for new devicetrees
  to specify this property, to keep backwards compatibility a range of
  0x00-0xff is assumed if not present)

EP mode:

• max-functions: maximum number of functions that can be configured

Example configuration:

pcie: pcie@dfc00000 {
    compatible = "snps,dw-pcie";
    reg = <0xdfc00000 0x0001000>, /* IP registers */
          <0xd0000000 0x0002000>; /* Configuration space */
    reg-names = "dbi", "config";
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
          0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
    interrupts = <25>, <24>;
    #interrupt-cells = <1>;
    num-lanes = <1>;
};

or
pcie: pcie@dfc00000 {
compatible = “snps,dw-pcie-ep”;
reg = <0xdfc00000 0x0001000>, /* IP registers 1 /
<0xdfc01000 0x0001000>, / IP registers 2 /
<0xd0000000 0x2000000>; / Configuration space */
reg-names = “dbi”, “dbi2”, “addr_space”;
num-ib-windows = <6>;
num-ob-windows = <2>;
num-lanes = <1>;
};