Analog Devices ADF4350/ADF4351 device driver
Required properties:
- compatible: Should be one of
* “adi,adf4350”: When using the ADF4350 device
* “adi,adf4351”: When using the ADF4351 device
- reg: SPI chip select numbert for the device
- spi-max-frequency: Max SPI frequency to use (< 20000000)
- clocks: From common clock binding. Clock is phandle to clock for
ADF435x Reference Clock (CLKIN).
Optional properties:
- gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
pll lock state is tested upon read.
- adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
- adi,power-up-frequency: If set in Hz the PLL tunes to
the desired frequency on probe.
- adi,reference-div-factor: If set the driver skips dynamic calculation
and uses this default value instead.
- adi,reference-doubler-enable: Enables reference doubler.
- adi,reference-div2-enable: Enables reference divider.
- adi,phase-detector-polarity-positive-enable: Enables positive phase
detector polarity. Default = negative.
- adi,lock-detect-precision-6ns-enable: Enables 6ns lock detect precision.
Default = 10ns.
- adi,lock-detect-function-integer-n-enable: Enables lock detect
for integer-N mode. Default = factional-N mode.
- adi,charge-pump-current: Charge pump current in mA.
Default = 2500mA.
- adi,muxout-select: On chip multiplexer output selection.
Valid values for the multiplexer output are:
0: Three-State Output (default)
1: DVDD
2: DGND
3: R-Counter output
4: N-Divider output
5: Analog lock detect
6: Digital lock detect
- adi,low-spur-mode-enable: Enables low spur mode.
Default = Low noise mode.
- adi,cycle-slip-reduction-enable: Enables cycle slip reduction.
- adi,charge-cancellation-enable: Enabled charge pump
charge cancellation for integer-N modes.
- adi,anti-backlash-3ns-enable: Enables 3ns antibacklash pulse width
for integer-N modes.
- adi,band-select-clock-mode-high-enable: Enables faster band
selection logic.
- adi,12bit-clk-divider: Clock divider value used when
adi,12bit-clkdiv-mode != 0
- adi,clk-divider-mode:
Valid values for the clkdiv mode are:
0: Clock divider off (default)
1: Fast lock enable
2: Phase resync enable
- adi,aux-output-enable: Enables auxiliary RF output.
- adi,aux-output-fundamental-enable: Selects fundamental VCO output on
the auxiliary RF output. Default = Output of RF dividers.
- adi,mute-till-lock-enable: Enables Mute-Till-Lock-Detect function.
- adi,output-power: Output power selection.
Valid values for the power mode are:
0: -4dBm (default)
1: -1dBm
2: +2dBm
3: +5dBm
- adi,aux-output-power: Auxiliary output power selection.
Valid values for the power mode are:
0: -4dBm (default)
1: -1dBm
2: +2dBm
3: +5dBm
Example:
lo_pll0_rx_adf4351: adf4351-rx-lpc@4 {
compatible = “adi,adf4351”;
reg = <4>;
spi-max-frequency = <10000000>;
clocks = <&clk0_ad9523 9>;
clock-names = “clkin”;
adi,channel-spacing = <10000>;
adi,power-up-frequency = <2400000000>;
adi,phase-detector-polarity-positive-enable;
adi,charge-pump-current = <2500>;
adi,output-power = <3>;
adi,mute-till-lock-enable;
};
