Kernel-4.18.0-80.el8_8250

published: updated: Kernel_4.18.0-80.el8_内核文档
  • UART (Universal Asynchronous Receiver/Transmitter)

Required properties:

  • compatible : one of:
    • “ns8250”
    • “ns16450”
    • “ns16550a”
    • “ns16550”
    • “ns16750”
    • “ns16850”
    • For Tegra20, must contain “nvidia,tegra20-uart”
    • For other Tegra, must contain ‘“nvidia,-uart”,
      “nvidia,tegra20-uart”‘ where is tegra30, tegra114, tegra124,
      tegra132, or tegra210.
    • “nxp,lpc3220-uart”
    • “ralink,rt2880-uart”
    • For MediaTek BTIF, must contain ‘“mediatek,-btif”,
      “mediatek,mtk-btif”‘ where is mt7622, mt7623.
    • “altr,16550-FIFO32”
    • “altr,16550-FIFO64”
    • “altr,16550-FIFO128”
    • “fsl,16550-FIFO64”
    • “fsl,ns16550”
    • “ti,da830-uart”
    • “aspeed,ast2400-vuart”
    • “aspeed,ast2500-vuart”
    • “nuvoton,npcm750-uart”
    • “serial” if the port type is unknown.
  • reg : offset and length of the register set for the device.
  • interrupts : should contain uart interrupt.
  • clock-frequency : the input clock frequency for the UART
    or
    clocks phandle to refer to the clk used as per Documentation/devicetree
    /bindings/clock/clock-bindings.txt

Optional properties:

  • current-speed : the current active speed of the UART.
  • reg-offset : offset to apply to the mapbase from the start of the registers.
  • reg-shift : quantity to shift the register offsets by.
  • reg-io-width : the size (in bytes) of the IO accesses that should be
    performed on the device. There are some systems that require 32-bit
    accesses to the UART (e.g. TI davinci).
  • used-by-rtas : set to indicate that the port is in use by the OpenFirmware
    RTAS and should not be registered.
  • no-loopback-test: set to indicate that the port does not implements loopback
    test mode
  • fifo-size: the fifo size of the UART.
  • auto-flow-control: one way to enable automatic flow control support. The
    driver is allowed to detect support for the capability even without this
    property.
  • tx-threshold: Specify the TX FIFO low water indication for parts with
    programmable TX FIFO thresholds.
  • resets : phandle + reset specifier pairs

Note:

  • fsl,ns16550:

    Freescale DUART is very similar to the PC16552D (and to a
    pair of NS16550A), albeit with some nonstandard behavior such as
    erratum A-004737 (relating to incorrect BRK handling).

    Represents a single port that is compatible with the DUART found
    on many Freescale chips (examples include mpc8349, mpc8548,
    mpc8641d, p4080 and ls2085a).

Example:

uart@80230000 {
    compatible = "ns8250";
    reg = <0x80230000 0x100>;
    clock-frequency = <3686400>;
    interrupts = <10>;
    reg-shift = <2>;
};

oosTech by Sam Lee