Kernel-3.10.0-957.el7_sunxi

published: updated: Kernel_3.10.0-957.el7_内核文档

Device Tree Clock bindings for arch-sunxi

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

  • compatible : shall be one of the following:
    “allwinner,sun4i-osc-clk” - for a gatable oscillator
    “allwinner,sun4i-pll1-clk” - for the main PLL clock
    “allwinner,sun4i-cpu-clk” - for the CPU multiplexer clock
    “allwinner,sun4i-axi-clk” - for the AXI clock
    “allwinner,sun4i-axi-gates-clk” - for the AXI gates
    “allwinner,sun4i-ahb-clk” - for the AHB clock
    “allwinner,sun4i-ahb-gates-clk” - for the AHB gates
    “allwinner,sun4i-apb0-clk” - for the APB0 clock
    “allwinner,sun4i-apb0-gates-clk” - for the APB0 gates
    “allwinner,sun4i-apb1-clk” - for the APB1 clock
    “allwinner,sun4i-apb1-mux-clk” - for the APB1 clock muxing
    “allwinner,sun4i-apb1-gates-clk” - for the APB1 gates

Required properties for all clocks:

  • reg : shall be the control register address for the clock.
  • clocks : shall be the input parent clock(s) phandle for the clock
  • #clock-cells : from common clock binding; shall be set to 0 except for
    “allwinner,sun4i-*-gates-clk” where it shall be set to 1

Additionally, “allwinner,sun4i-*-gates-clk” clocks require:

  • clock-output-names : the corresponding gate names that the clock controls

For example:

osc24M: osc24M@01c20050 {
#clock-cells = <0>;
compatible = “allwinner,sun4i-osc-clk”;
reg = <0x01c20050 0x4>;
clocks = <&osc24M_fixed>;
};

pll1: pll1@01c20000 {
#clock-cells = <0>;
compatible = “allwinner,sun4i-pll1-clk”;
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
};

cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = “allwinner,sun4i-cpu-clk”;
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>;
};

Gate clock outputs

The “allwinner,sun4i-*-gates-clk” clocks provide several gatable outputs;
their corresponding offsets as present on sun4i are listed below. Note that
some of these gates are not present on sun5i.

  • AXI gates (“allwinner,sun4i-axi-gates-clk”)

    DRAM 0

  • AHB gates (“allwinner,sun4i-ahb-gates-clk”)

    USB0 0
    EHCI0 1
    OHCI0 2*
    EHCI1 3
    OHCI1 4*
    SS 5
    DMA 6
    BIST 7
    MMC0 8
    MMC1 9
    MMC2 10
    MMC3 11
    MS 12**
    NAND 13
    SDRAM 14

    ACE 16
    EMAC 17
    TS 18

    SPI0 20
    SPI1 21
    SPI2 22
    SPI3 23
    PATA 24
    SATA 25**
    GPS 26*

    VE 32
    TVD 33
    TVE0 34
    TVE1 35
    LCD0 36
    LCD1 37

    CSI0 40
    CSI1 41

    HDMI 43
    DE_BE0 44
    DE_BE1 45
    DE_FE0 46
    DE_FE1 47

    MP 50

    MALI400 52

  • APB0 gates (“allwinner,sun4i-apb0-gates-clk”)

    CODEC 0
    SPDIF 1*
    AC97 2
    IIS 3

    PIO 5
    IR0 6
    IR1 7

    KEYPAD 10

  • APB1 gates (“allwinner,sun4i-apb1-gates-clk”)

    I2C0 0
    I2C1 1
    I2C2 2

    CAN 4
    SCR 5
    PS20 6
    PS21 7

    UART0 16
    UART1 17
    UART2 18
    UART3 19
    UART4 20
    UART5 21
    UART6 22
    UART7 23

Notation:
[*]: The datasheet didn’t mention these, but they are present on AW code
[**]: The datasheet had this marked as “NC” but they are used on AW code

oosTech by Sam Lee