Kernel-3.10.0-957.el7_nvidia,tegra20-pmc

published: updated: Kernel_3.10.0-957.el7_内核文档

NVIDIA Tegra Power Management Controller (PMC)

The PMC block interacts with an external Power Management Unit. The PMC
mostly controls the entry and exit of the system from different sleep
modes. It provides power-gating controllers for SoC and CPU power-islands.

Required properties:

  • name : Should be pmc
  • compatible : Should contain “nvidia,tegra-pmc”.
  • reg : Offset and length of the register set for the device
  • clocks : Must contain an entry for each entry in clock-names.
  • clock-names : Must include the following entries:
    “pclk” (The Tegra clock of that name),
    “clk32k_in” (The 32KHz clock input to Tegra).

Optional properties:

  • nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
    The PMU is an external Power Management Unit, whose interrupt output
    signal is fed into the PMC. This signal is optionally inverted, and then
    fed into the ARM GIC. The PMC is not involved in the detection or
    handling of this interrupt signal, merely its inversion.
  • nvidia,suspend-mode : The suspend mode that the platform should use.
    Valid values are 0, 1 and 2:
    0 (LP0): CPU + Core voltage off and DRAM in self-refresh
    1 (LP1): CPU voltage off and DRAM in self-refresh
    2 (LP2): CPU voltage off
  • nvidia,core-power-req-active-high : Boolean, core power request active-high
  • nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
  • nvidia,combined-power-req : Boolean, combined power request for CPU & Core
  • nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
             is enabled.

Required properties when nvidia,suspend-mode is specified:

  • nvidia,cpu-pwr-good-time : CPU power good time in uS.
  • nvidia,cpu-pwr-off-time : CPU power off time in uS.
  • nvidia,core-pwr-good-time : 
                Core power good time in uS.
  • nvidia,core-pwr-off-time : Core power off time in uS.

Required properties when nvidia,suspend-mode=<0>:

  • nvidia,lp0-vec : Starting address and length of LP0 vector
    The LP0 vector contains the warm boot code that is executed by AVP when
    resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
    processor and always being the first boot processor when chip is power on
    or resume from deep sleep mode. When the system is resumed from the deep
    sleep mode, the warm boot code will restore some PLLs, clocks and then
    bring up CPU0 for resuming the system.

Example:

/ SoC dts including file
pmc@7000f400 {
compatible = “nvidia,tegra20-pmc”;
reg = <0x7000e400 0x400>;
clocks = <&tegra_car 110>, <&clk32k_in>;
clock-names = “pclk”, “clk32k_in”;
nvidia,invert-interrupt;
nvidia,suspend-mode = <1>;
nvidia,cpu-pwr-good-time = <2000>;
nvidia,cpu-pwr-off-time = <100>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <458>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
nvidia,lp0-vec = <0xbdffd000 0x2000>;
};

/ Tegra board dts file
{
…
clocks {
compatible = “simple-bus”;
#address-cells = <1>;
#size-cells = <0>;

    clk32k_in: clock {
        compatible = "fixed-clock";
        reg=<0>;
        #clock-cells = <0>;
        clock-frequency = <32768>;
    };
};
...

};

oosTech by Sam Lee