Kernel-3.10.0-957.el7_nvidia,tegra20-host1x

NVIDIA Tegra host1x

Required properties:

• compatible: “nvidia,tegra-host1x”
• reg: Physical base address and length of the controller’s registers.
• interrupts: The interrupt outputs from the controller.
• #address-cells: The number of cells used to represent physical base addresses
  in the host1x address space. Should be 1.
• #size-cells: The number of cells used to represent the size of an address
  range in the host1x address space. Should be 1.
• ranges: The mapping of the host1x address space to the CPU address space.

The host1x top-level node defines a number of children, each representing one
of the following host1x client modules:

• mpe: video encoder

  Required properties:

  • compatible: “nvidia,tegra-mpe”
  • reg: Physical base address and length of the controller’s registers.
  • interrupts: The interrupt outputs from the controller.

• vi: video input

  Required properties:

  • compatible: “nvidia,tegra-vi”
  • reg: Physical base address and length of the controller’s registers.
  • interrupts: The interrupt outputs from the controller.

• epp: encoder pre-processor

  Required properties:

  • compatible: “nvidia,tegra-epp”
  • reg: Physical base address and length of the controller’s registers.
  • interrupts: The interrupt outputs from the controller.

• isp: image signal processor

  Required properties:

  • compatible: “nvidia,tegra-isp”
  • reg: Physical base address and length of the controller’s registers.
  • interrupts: The interrupt outputs from the controller.

• gr2d: 2D graphics engine

  Required properties:

  • compatible: “nvidia,tegra-gr2d”
  • reg: Physical base address and length of the controller’s registers.
  • interrupts: The interrupt outputs from the controller.

• gr3d: 3D graphics engine

  Required properties:

  • compatible: “nvidia,tegra-gr3d”
  • reg: Physical base address and length of the controller’s registers.

• dc: display controller

  Required properties:

  • compatible: “nvidia,tegra-dc”
  • reg: Physical base address and length of the controller’s registers.
  • interrupts: The interrupt outputs from the controller.

  Each display controller node has a child node, named “rgb”, that represents
  the RGB output associated with the controller. It can take the following
  optional properties:

  • nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  • nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  • nvidia,edid: supplies a binary EDID blob

• hdmi: High Definition Multimedia Interface

  Required properties:

  • compatible: “nvidia,tegra-hdmi”
  • reg: Physical base address and length of the controller’s registers.
  • interrupts: The interrupt outputs from the controller.
  • vdd-supply: regulator for supply voltage
  • pll-supply: regulator for PLL

  Optional properties:

  • nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  • nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  • nvidia,edid: supplies a binary EDID blob

• tvo: TV encoder output

  Required properties:

  • compatible: “nvidia,tegra-tvo”
  • reg: Physical base address and length of the controller’s registers.
  • interrupts: The interrupt outputs from the controller.

• dsi: display serial interface

  Required properties:

  • compatible: “nvidia,tegra-dsi”
  • reg: Physical base address and length of the controller’s registers.

Example:

/ {
…

host1x {
    compatible = "nvidia,tegra20-host1x", "simple-bus";
    reg = <0x50000000 0x00024000>;
    interrupts = <0 65 0x04   /* mpcore syncpt */
              0 67 0x04>; /* mpcore general */

    #address-cells = <1>;
    #size-cells = <1>;

    ranges = <0x54000000 0x54000000 0x04000000>;

    mpe {
        compatible = "nvidia,tegra20-mpe";
        reg = <0x54040000 0x00040000>;
        interrupts = <0 68 0x04>;
    };

    vi {
        compatible = "nvidia,tegra20-vi";
        reg = <0x54080000 0x00040000>;
        interrupts = <0 69 0x04>;
    };

    epp {
        compatible = "nvidia,tegra20-epp";
        reg = <0x540c0000 0x00040000>;
        interrupts = <0 70 0x04>;
    };

    isp {
        compatible = "nvidia,tegra20-isp";
        reg = <0x54100000 0x00040000>;
        interrupts = <0 71 0x04>;
    };

    gr2d {
        compatible = "nvidia,tegra20-gr2d";
        reg = <0x54140000 0x00040000>;
        interrupts = <0 72 0x04>;
    };

    gr3d {
        compatible = "nvidia,tegra20-gr3d";
        reg = <0x54180000 0x00040000>;
    };

    dc@54200000 {
        compatible = "nvidia,tegra20-dc";
        reg = <0x54200000 0x00040000>;
        interrupts = <0 73 0x04>;

        rgb {
            status = "disabled";
        };
    };

    dc@54240000 {
        compatible = "nvidia,tegra20-dc";
        reg = <0x54240000 0x00040000>;
        interrupts = <0 74 0x04>;

        rgb {
            status = "disabled";
        };
    };

    hdmi {
        compatible = "nvidia,tegra20-hdmi";
        reg = <0x54280000 0x00040000>;
        interrupts = <0 75 0x04>;
        status = "disabled";
    };

    tvo {
        compatible = "nvidia,tegra20-tvo";
        reg = <0x542c0000 0x00040000>;
        interrupts = <0 76 0x04>;
        status = "disabled";
    };

    dsi {
        compatible = "nvidia,tegra20-dsi";
        reg = <0x54300000 0x00040000>;
        status = "disabled";
    };
};

...

};