Kernel-4.18.0-80.el8_vt8500

Device Tree Clock bindings for arch-vt8500

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

• compatible : shall be one of the following:
  “via,vt8500-pll-clock” - for a VT8500/WM8505 PLL clock
  “wm,wm8650-pll-clock” - for a WM8650 PLL clock
  “wm,wm8750-pll-clock” - for a WM8750 PLL clock
  “wm,wm8850-pll-clock” - for a WM8850 PLL clock
  “via,vt8500-device-clock” - for a VT/WM device clock

Required properties for PLL clocks:

• reg : shall be the control register offset from PMC base for the pll clock.
• clocks : shall be the input parent clock phandle for the clock. This should
  be the reference clock.
• #clock-cells : from common clock binding; shall be set to 0.

Required properties for device clocks:

• clocks : shall be the input parent clock phandle for the clock. This should
  be a pll output.
• #clock-cells : from common clock binding; shall be set to 0.

Device Clocks

Device clocks are required to have one or both of the following sets of
properties:

Gated device clocks:

Required properties:

• enable-reg : shall be the register offset from PMC base for the enable
  register.
• enable-bit : shall be the bit within enable-reg to enable/disable the clock.

Divisor device clocks:

Required property:

• divisor-reg : shall be the register offset from PMC base for the divisor
  register.
  Optional property:
• divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
  if not specified.

For example:

ref25: ref25M {
#clock-cells = <0>;
compatible = “fixed-clock”;
clock-frequency = <25000000>;
};

plla: plla {
#clock-cells = <0>;
compatible = “wm,wm8650-pll-clock”;
clocks = <&ref25>;
reg = <0x200>;
};

sdhc: sdhc {
#clock-cells = <0>;
compatible = “via,vt8500-device-clock”;
clocks = <&pllb>;
divisor-reg = <0x328>;
divisor-mask = <0x3f>;
enable-reg = <0x254>;
enable-bit = <18>;
};