Kernel-4.18.0-80.el8_nvidia,tegra30-mc

NVIDIA Tegra Memory Controller device tree bindings

memory-controller node

Required properties:

• compatible: Should be “nvidia,tegra-mc”
• reg: Physical base address and length of the controller’s registers.
• clocks: Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
• clock-names: Must include the following entries:
  • mc: the module’s clock input
• interrupts: The interrupt outputs from the controller.
• #reset-cells : Should be 1. This cell represents memory client module ID.
  The assignments may be found in header file <dt-bindings/memory/tegra30-mc.h>
  or in the TRM documentation.

Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:

• #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
  the SWGROUP of the master.

This device implements an IOMMU that complies with the generic IOMMU binding.
See ../iommu/iommu.txt for details.

emc-timings subnode

The node should contain a “emc-timings” subnode for each supported RAM type (see field RAM_CODE in
register PMC_STRAPPING_OPT_A).

Required properties for “emc-timings” nodes :

• nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for.

timing subnode

Each “emc-timings” node should contain a subnode for every supported EMC clock rate.

Required properties for timing nodes :

• clock-frequency : Should contain the memory clock rate in Hz.

• nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC
  (see section “15.6.1 MC Registers” in the TRM), these are the registers whose values need to be
  specified, according to the board documentation:

  MC_EMEM_ARB_CFG
  MC_EMEM_ARB_OUTSTANDING_REQ
  MC_EMEM_ARB_TIMING_RCD
  MC_EMEM_ARB_TIMING_RP
  MC_EMEM_ARB_TIMING_RC
  MC_EMEM_ARB_TIMING_RAS
  MC_EMEM_ARB_TIMING_FAW
  MC_EMEM_ARB_TIMING_RRD
  MC_EMEM_ARB_TIMING_RAP2PRE
  MC_EMEM_ARB_TIMING_WAP2PRE
  MC_EMEM_ARB_TIMING_R2R
  MC_EMEM_ARB_TIMING_W2W
  MC_EMEM_ARB_TIMING_R2W
  MC_EMEM_ARB_TIMING_W2R
  MC_EMEM_ARB_DA_TURNS
  MC_EMEM_ARB_DA_COVERS
  MC_EMEM_ARB_MISC0
  MC_EMEM_ARB_MISC1
  MC_EMEM_ARB_RING1_THROTTLE

Example SoC include file:

/ {
mc: memory-controller@70019000 {
compatible = “nvidia,tegra124-mc”;
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
clock-names = “mc”;

    interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

    #iommu-cells = <1>;
    #reset-cells = <1>;
};

sdhci@700b0000 {
    compatible = "nvidia,tegra124-sdhci";
    ...
    iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
    resets = <&mc TEGRA124_MC_RESET_SDMMC1>;
};

};

Example board file:

/ {
memory-controller@70019000 {
emc-timings-3 {
nvidia,ram-code = <3>;

        timing-12750000 {
            clock-frequency = <12750000>;

            nvidia,emem-configuration = <
                0x40040001 /* MC_EMEM_ARB_CFG */
                0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
                0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
                0x00000001 /* MC_EMEM_ARB_TIMING_RP */
                0x00000002 /* MC_EMEM_ARB_TIMING_RC */
                0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
                0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
                0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
                0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
                0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
                0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
                0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
                0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
                0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
                0x06030203 /* MC_EMEM_ARB_DA_TURNS */
                0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
                0x77e30303 /* MC_EMEM_ARB_MISC0 */
                0x70000f03 /* MC_EMEM_ARB_MISC1 */
                0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
            >;
        };
    };
};

};