Kernel-4.18.0-80.el8_mscc-mii

Microsemi MII Management Controller (MIIM) / MDIO

Properties:

• compatible: must be “mscc,ocelot-miim”
• reg: The base address of the MDIO bus controller register bank. Optionally, a
  second register bank can be defined if there is an associated reset register
  for internal PHYs
• #address-cells: Must be <1>.
• #size-cells: Must be <0>. MDIO addresses have no size component.
• interrupts: interrupt specifier (refer to the interrupt binding)

Typically an MDIO bus might have several children.

Example:
mdio@107009c {
#address-cells = <1>;
#size-cells = <0>;
compatible = “mscc,ocelot-miim”;
reg = <0x107009c 0x36>, <0x10700f0 0x8>;
interrupts = <14>;

    phy0: ethernet-phy@0 {
        reg = <0>;
    };
};