Kernel-4.18.0-80.el8_mdio-mux

Common MDIO bus multiplexer/switch properties.

An MDIO bus multiplexer/switch will have several child busses that are
numbered uniquely in a device dependent manner. The nodes for an MDIO
bus multiplexer/switch will have one child node for each child bus.

Required properties:

• #address-cells = <1>;
• #size-cells = <0>;

Optional properties:

• mdio-parent-bus : phandle to the parent MDIO bus.

• Other properties specific to the multiplexer/switch hardware.

Required properties for child nodes:

• #address-cells = <1>;
• #size-cells = <0>;
• reg : The sub-bus number.

Example :

/* The parent MDIO bus. */
smi1: mdio@1180000001900 {
    compatible = "cavium,octeon-3860-mdio";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x11800 0x00001900 0x0 0x40>;
};

/*
   An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
   pair of GPIO lines.  Child busses 2 and 3 populated with 4
   PHYs each.
 */
mdio-mux {
    compatible = "mdio-mux-gpio";
    gpios = <&gpio1 3 0>, <&gpio1 4 0>;
    mdio-parent-bus = <&smi1>;
    #address-cells = <1>;
    #size-cells = <0>;

    mdio@2 {
        reg = <2>;
        #address-cells = <1>;
        #size-cells = <0>;

        phy11: ethernet-phy@1 {
            reg = <1>;
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <10 8>; /* Pin 10, active low */
        };
        phy12: ethernet-phy@2 {
            reg = <2>;
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <10 8>; /* Pin 10, active low */
        };
        phy13: ethernet-phy@3 {
            reg = <3>;
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <10 8>; /* Pin 10, active low */
        };
        phy14: ethernet-phy@4 {
            reg = <4>;
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <10 8>; /* Pin 10, active low */
        };
    };

    mdio@3 {
        reg = <3>;
        #address-cells = <1>;
        #size-cells = <0>;

        phy21: ethernet-phy@1 {
            reg = <1>;
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <12 8>; /* Pin 12, active low */
        };
        phy22: ethernet-phy@2 {
            reg = <2>;
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <12 8>; /* Pin 12, active low */
        };
        phy23: ethernet-phy@3 {
            reg = <3>;
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <12 8>; /* Pin 12, active low */
        };
        phy24: ethernet-phy@4 {
            reg = <4>;
            marvell,reg-init = <3 0x10 0 0x5777>,
                <3 0x11 0 0x00aa>,
                <3 0x12 0 0x4105>,
                <3 0x13 0 0x0a60>;
            interrupt-parent = <&gpio>;
            interrupts = <12 8>; /* Pin 12, active low */
        };
    };
};