Kernel-4.18.0-80.el8_lpc32xx-slc

NXP LPC32xx SoC NAND SLC controller

Required properties:

• compatible: “nxp,lpc3220-slc”
• reg: Address and size of the controller
• nand-on-flash-bbt: Use bad block table on flash
• gpios: GPIO specification for NAND write protect

The following required properties are very controller specific. See the LPC32xx
User Manual:

• nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
• nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
  (The following values are specified in Hz, to make them independent of actual
  clock speed:)
• nxp,wwidth: Write pulse width (W_WIDTH)
• nxp,whold: Write hold time (W_HOLD)
• nxp,wsetup: Write setup time (W_SETUP)
• nxp,rwidth: Read pulse width (R_WIDTH)
• nxp,rhold: Read hold time (R_HOLD)
• nxp,rsetup: Read setup time (R_SETUP)

Optional subnodes:

• Partitions, see Documentation/devicetree/bindings/mtd/partition.txt

Example:

slc: flash@20020000 {
    compatible = "nxp,lpc3220-slc";
    reg = <0x20020000 0x1000>;
    #address-cells = <1>;
    #size-cells = <1>;

    nxp,wdr-clks = <14>;
    nxp,wwidth = <40000000>;
    nxp,whold = <100000000>;
    nxp,wsetup = <100000000>;
    nxp,rdr-clks = <14>;
    nxp,rwidth = <40000000>;
    nxp,rhold = <66666666>;
    nxp,rsetup = <100000000>;
    nand-on-flash-bbt;
    gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */

    mtd0@00000000 {
        label = "phy3250-boot";
        reg = <0x00000000 0x00064000>;
        read-only;
    };

    ...

};