Kernel-4.18.0-80.el8_lpc1850-dmamux

NXP LPC18xx/43xx DMA MUX (DMA request router)

Required properties:

• compatible: “nxp,lpc1850-dmamux”
• reg: Memory map for accessing module
• #dma-cells: Should be set to <3>.

    * 1st cell contain the master dma request signal
    * 2nd cell contain the mux value (0-3) for the peripheral
    * 3rd cell contain either 1 or 2 depending on the AHB
      master used.
  

• dma-requests: Number of DMA requests for the mux
• dma-masters: phandle pointing to the DMA controller

The DMA controller node need to have the following poroperties:

• dma-requests: Number of DMA requests the controller can handle

Example:

dmac: dma@40002000 {
compatible = “nxp,lpc1850-gpdma”, “arm,pl080”, “arm,primecell”;
arm,primecell-periphid = <0x00041080>;
reg = <0x40002000 0x1000>;
interrupts = <2>;
clocks = <&ccu1 CLK_CPU_DMA>;
clock-names = “apb_pclk”;
#dma-cells = <2>;
dma-channels = <8>;
dma-requests = <16>;
lli-bus-interface-ahb1;
lli-bus-interface-ahb2;
mem-bus-interface-ahb1;
mem-bus-interface-ahb2;
memcpy-burst-size = <256>;
memcpy-bus-width = <32>;
};

dmamux: dma-mux {
compatible = “nxp,lpc1850-dmamux”;
#dma-cells = <3>;
dma-requests = <64>;
dma-masters = <&dmac>;
};

uart0: serial@40081000 {
compatible = “nxp,lpc1850-uart”, “ns16550a”;
reg = <0x40081000 0x1000>;
reg-shift = <2>;
interrupts = <24>;
clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
clock-names = “uartclk”, “reg”;
dmas = <&dmamux 1 1 2
&dmamux 2 1 2>;
dma-names = “tx”, “rx”;
};