Kernel-4.18.0-80.el8_fsl,imx7ulp-pinctrl

• Freescale i.MX7ULP IOMUX Controller

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
ports and IOMUXC DDR for DDR interface.

Note:
This binding doc is only for the IOMUXC1 support in A7 Domain and it only
supports generic pin config.

Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
binding.

=== Pin Controller Node ===

Required properties:

• compatible: “fsl,imx7ulp-iomuxc1”
• reg: Should contain the base physical address and size of the iomuxc

    registers.
  

=== Pin Configuration Node ===

• pinmux: One integers array, represents a group of pins mux setting.
  The format is pinmux = , PIN_FUNC_ID is a pin working on
  a specific function.

  NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
  and config register as follows:

  Refer to imx7ulp-pinfunc.h in in device tree source folder for all
  available imx7ulp PIN_FUNC_ID.

Optional Properties:

• drive-strength Integer. Controls Drive Strength

                0: Standard
                1: Hi Driver
  

• drive-push-pull Bool. Enable Pin Push-pull
• drive-open-drain Bool. Enable Pin Open-drian
• slew-rate: Integer. Controls Slew Rate

                0: Standard
                1: Slow
  

• bias-disable: Bool. Pull disabled
• bias-pull-down: Bool. Pull down on pin
• bias-pull-up: Bool. Pull up on pin

Examples:
#include “imx7ulp-pinfunc.h”

/* Pin Controller Node */
iomuxc1: iomuxc@40ac0000 {
compatible = “fsl,imx7ulp-iomuxc1”;
reg = <0x40ac0000 0x1000>;

/* Pin Configuration Node */
pinctrl_lpuart4: lpuart4grp {
    pinmux = <
        IMX7ULP_PAD_PTC3__LPUART4_RX
        IMX7ULP_PAD_PTC2__LPUART4_TX
    >;
    bias-pull-up;
};

};