Kernel-4.18.0-80.el8_exynos-usb

Samsung Exynos SoC USB controller

The USB devices interface with USB controllers on Exynos SOCs.
The device node has following properties.

EHCI
Required properties:

• compatible: should be “samsung,exynos4210-ehci” for USB 2.0
  EHCI controller in host mode.
• reg: physical base address of the controller and length of memory mapped
  region.
• interrupts: interrupt number to the cpu.
• clocks: from common clock binding: handle to usb clock.
• clock-names: from common clock binding: Shall be “usbhost”.
• port: if in the SoC there are EHCI phys, they should be listed here.
  One phy per port. Each port should have following entries:
  • reg: port number on EHCI controller, e.g

     On Exynos5250, port 0 is USB2.0 otg phy
            port 1 is HSIC phy0
            port 2 is HSIC phy1
    

  • phys: from the Generic PHY bindings; specifying phy used by port.

Optional properties:

• samsung,vbus-gpio: if present, specifies the GPIO that
  needs to be pulled up for the bus to be powered.

Example:

usb@12110000 {
    compatible = "samsung,exynos4210-ehci";
    reg = <0x12110000 0x100>;
    interrupts = <0 71 0>;
    samsung,vbus-gpio = <&gpx2 6 1 3 3>;

    clocks = <&clock 285>;
    clock-names = "usbhost";

    #address-cells = <1>;
    #size-cells = <0>;
    port@0 {
        reg = <0>;
        phys = <&usb2phy 1>;
    };
};

OHCI
Required properties:

• compatible: should be “samsung,exynos4210-ohci” for USB 2.0
  OHCI companion controller in host mode.
• reg: physical base address of the controller and length of memory mapped
  region.
• interrupts: interrupt number to the cpu.
• clocks: from common clock binding: handle to usb clock.
• clock-names: from common clock binding: Shall be “usbhost”.
• port: if in the SoC there are OHCI phys, they should be listed here.
  One phy per port. Each port should have following entries:
  • reg: port number on OHCI controller, e.g

     On Exynos5250, port 0 is USB2.0 otg phy
            port 1 is HSIC phy0
            port 2 is HSIC phy1
    

  • phys: from the Generic PHY bindings, specifying phy used by port.

Example:
usb@12120000 {
compatible = “samsung,exynos4210-ohci”;
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;

    clocks = <&clock 285>;
    clock-names = "usbhost";

    #address-cells = <1>;
    #size-cells = <0>;
    port@0 {
        reg = <0>;
        phys = <&usb2phy 1>;
    };

};

DWC3
Required properties:

• compatible: should be one of the following -

      "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
                   Exynos5250/5420.
      "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
  

• #address-cells, #size-cells : should be ‘1’ if the device has sub-nodes

            with 'reg' property.
  

• ranges: allows valid 1:1 translation between child’s address space and

  parent's address space
  

• clocks: Clock IDs array as required by the controller.
• clock-names: names of clocks correseponding to IDs in the clock property
• vdd10-supply: 1.0V powr supply
• vdd33-supply: 3.0V/3.3V power supply

Sub-nodes:
The dwc3 core should be added as subnode to Exynos dwc3 glue.

• dwc3 :
  The binding details of dwc3 can be found in:
  Documentation/devicetree/bindings/usb/dwc3.txt

Example:
usb@12000000 {
compatible = “samsung,exynos5250-dwusb3”;
clocks = <&clock 286>;
clock-names = “usbdrd30”;
#address-cells = <1>;
#size-cells = <1>;
ranges;
vdd10-supply = <&ldo11_reg>;
vdd33-supply = <&ldo9_reg>;

    dwc3 {
        compatible = "synopsys,dwc3";
        reg = <0x12000000 0x10000>;
        interrupts = <0 72 0>;
        usb-phy = <&usb2_phy &usb3_phy>;
    };
};