Kernel-4.18.0-80.el8_arm,smmu

  • ARM System MMU Architecture Implementation

ARM SoCs may contain an implementation of the ARM System Memory
Management Unit Architecture, which can be used to provide 1 or 2 stages
of address translation to bus masters external to the CPU.

The SMMU may also raise interrupts in response to various fault
conditions.

** System MMU required properties:

  • compatible : Should be one of:

                      "arm,smmu-v1"
                      "arm,smmu-v2"
                      "arm,mmu-400"
                      "arm,mmu-401"
                      "arm,mmu-500"
                      "cavium,smmu-v2"
    
                depending on the particular implementation and/or the
                version of the architecture implemented.
    
  • reg : Base address and size of the SMMU.

  • #global-interrupts : The number of global interrupts exposed by the

                     device.
    
  • interrupts : Interrupt list, with the first #global-irqs entries

                corresponding to the global interrupts and any
                following entries corresponding to context interrupts,
                specified in order of their indexing by the SMMU.
    
                For SMMUv2 implementations, there must be exactly one
                interrupt per context bank. In the case of a single,
                combined interrupt, it must be listed multiple times.
    
  • #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt

                for details. With a value of 1, each IOMMU specifier
                represents a distinct stream ID emitted by that device
                into the relevant SMMU.
    
                SMMUs with stream matching support and complex masters
                may use a value of 2, where the second cell of the
                IOMMU specifier represents an SMR mask to combine with
                the ID in the first cell.  Care must be taken to ensure
                the set of matched IDs does not result in conflicts.
    

** System MMU optional properties:

  • dma-coherent : Present if page table walks made by the SMMU are

                cache coherent with the CPU.
    
                NOTE: this only applies to the SMMU itself, not
                masters connected upstream of the SMMU.
    
  • calxeda,smmu-secure-config-access : Enable proper handling of buggy

                implementations that always use secure access to
                SMMU configuration registers. In this case non-secure
                aliases of secure registers have to be used during
                SMMU configuration.
    
  • stream-match-mask : For SMMUs supporting stream matching and using

                #iommu-cells = <1>, specifies a mask of bits to ignore
        when matching stream IDs (e.g. this may be programmed
        into the SMRn.MASK field of every stream match register
        used). For cases where it is desirable to ignore some
                portion of every Stream ID (e.g. for certain MMU-500
                configurations given globally unique input IDs). This
                property is not valid for SMMUs using stream indexing,
                or using stream matching with #iommu-cells = <2>, and
                may be ignored if present in such cases.
    

** Deprecated properties:

  • mmu-masters (deprecated in favour of the generic “iommus” binding) :
                A list of phandles to device nodes representing bus
                masters for which the SMMU can provide a translation
                and their corresponding Stream IDs. Each device node
                linked from this list must have a "#stream-id-cells"
                property, indicating the number of Stream ID
                arguments associated with its phandle.
    

** Examples:

    /* SMMU with stream matching or stream indexing */
    smmu1: iommu {
            compatible = "arm,smmu-v1";
            reg = <0xba5e0000 0x10000>;
            #global-interrupts = <2>;
            interrupts = <0 32 4>,
                         <0 33 4>,
                         <0 34 4>, /* This is the first context interrupt */
                         <0 35 4>,
                         <0 36 4>,
                         <0 37 4>;
            #iommu-cells = <1>;
    };

    /* device with two stream IDs, 0 and 7 */
    master1 {
            iommus = <&smmu1 0>,
                     <&smmu1 7>;
    };


    /* SMMU with stream matching */
    smmu2: iommu {
            ...
            #iommu-cells = <2>;
    };

    /* device with stream IDs 0 and 7 */
    master2 {
            iommus = <&smmu2 0 0>,
                     <&smmu2 7 0>;
    };

    /* device with stream IDs 1, 17, 33 and 49 */
    master3 {
            iommus = <&smmu2 1 0x30>;
    };


    /* ARM MMU-500 with 10-bit stream ID input configuration */
    smmu3: iommu {
            compatible = "arm,mmu-500", "arm,smmu-v2";
            ...
            #iommu-cells = <1>;
            /* always ignore appended 5-bit TBU number */
            stream-match-mask = 0x7c00;
    };

    bus {
            /* bus whose child devices emit one unique 10-bit stream
               ID each, but may master through multiple SMMU TBUs */
            iommu-map = <0 &smmu3 0 0x400>;
            ...
    };