Kernel-4.18.0-80.el8_abilis,tb10x-ictl

TB10x Top Level Interrupt Controller

The Abilis TB10x SOC contains a custom interrupt controller. It performs
one-to-one mapping of external interrupt sources to CPU interrupts and
provides support for reconfigurable trigger modes.

Required properties

  • compatible: Should be “abilis,tb10x-ictl”
  • reg: specifies physical base address and size of register range.
  • interrupt-congroller: Identifies the node as an interrupt controller.
  • #interrupt cells: Specifies the number of cells used to encode an interrupt
    source connected to this controller. The value shall be 2.
  • interrupt-parent: Specifies the parent interrupt controller.
  • interrupts: Specifies the list of interrupt lines which are handled by
    the interrupt controller in the parent controller’s notation. Interrupts
    are mapped one-to-one to parent interrupts.

Example

intc: interrupt-controller { /* Parent interrupt controller /
interrupt-controller;
#interrupt-cells = <1>; /
For example below /
/
… */
};

tb10x_ictl: pic@2000 { /* TB10x interrupt controller */
compatible = “abilis,tb10x-ictl”;
reg = <0x2000 0x20>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29 30 31>;
};